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Name:____________________________
CMIS 310 – Summer 2011

1. (24 points) Consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming an instruction cycle similar to figure 4.1 in the commentary, i.e.:
?        a one clock cycle fetch
?        a one clock cycle decode
?        a four clock cycle execute
and a 50 instruction sequence:
??        no pipelining would require _____ clock cycles:

?        a scalar pipeline would require _____ clock cycles:

?        a superscalar pipeline with two parallel units would require ______ clock cycles:

2. (30 points) Show the layout of the specified cache for a CPU that can address 8M x 16 of memory. Give the layout of the bits per location and the total number of locations.
(Hint: Similar to Self-Assessment Question 6 and Discussion Topic 9)

a) The cache holds 128K x 16 of data and has the fully associative strategy

b) The cache holds 128K x 16 of data and has the direct mapped strategy

c) The cache holds 128K x 16 of data and has the two-way set-associative strategy

8 (12 points) Consider Poor Richard’s cache as described in Conference Topic 2. Assume that a 7th word from main memory location 010111 is read and stored in cache. The words themselves are represented by aaaa aaaa through gggg gggg since their actual value does not affect the rest of the problem.
a) Show the cache word that would be written into the proper location of the Fully Associative cache shown below. Italicize or line through the old cache word and bold and/ or shade-in the new cache word.
Table 1 – Fully Associative Cache
Address in Main Memory Tag
6 bits Data
8 bits Valid bit
1 bit 00 1101 (13)
00 1101 aaaa aaaa 1 00 1110 (14)
00 1110 bbbb bbbb 1 10 0001 (33)
10 0001 cccc cccc 1 10 0010 (34)
10 0010 dddd dddd 1 10 0011 (35)
10…